1. Field of the Invention
The invention relates to a semiconductor integrated circuit, and more specifically, to an electrostatic protection circuit between electrical sources and the internal circuitry of the semiconductor integrated circuit.
2. Description of Related Art
Electrostatic discharge effect occurs in almost all processes of testing, packaging and utilizing an integrated circuit. An efficient electrostatic protection circuit is therefore required to discharge the current stress, or the integrated circuit will be damaged. Referring to FIG. 1, a conventional electrostatic protection circuit is arranged near an input/output pad 10 which connects to the internal circuitry (or core circuitry) 12 of the integrated circuit. The electrostatic protection circuit includes two protection elements 14 and 16, which connect between a voltage source VDD and the input/output pad 10, and between the input/output pad 10 and another voltage source VSS, respectively. The protection elements are, for example, diodes or MOS transistors. In general, the voltage source VDD provides a voltage of 5 V or 3.3 V, whereas the voltage source VSS is 0 V.
However, as the protection elements 14 and 16 of the conventional protection circuit provide direct discharge paths between the voltage source VDD and the input/output pad 10, and between the input/output pad 10 and the voltage source VSS, the discharge current will pull up the voltage level of the voltage sources VDD and VSS when stress is applied thereon, thereby damaging the internal circuitry 12, subsequently.
As X. Guggenmos proposed in "A New ESD Protection Concept for VLSI CMOS Circuits Avoiding Circuit Stressing," EOS/ESD Symp. Proc. EOS-13, 1991, pp.74-82, the stress on the voltage sources VDD and VSS can be reduced by introducing an NMOS transistor in the protection circuit. Referring to FIG. 1, the NMOS transistor 18 is connected between the voltage sources VDD and VSS. The drain of the NMOS transistor is connected to voltage source VDD, whereas the gate and source are connected to the voltage source VSS. The NMOS transistor 18 therefore provides a direct current path between the two voltage sources VDD and VSS.
The aforementioned modification of the protection circuit, however, occupies a large area since the NMOS transistor requires a channel width of about 4000-5000 .mu.m. The protection circuit can hardly be assembled with highly-integrated small-dimension semiconductor devices. Therefore, an effective and small protection circuit is required.